The present invention relates to a heterojunction field effect transistor and a method of fabricating the same.
A heterojunction field effect transistor (HFET) is also called, e.g., a high electron mobility transistor (HEMT) or a modulation dope field effect transistor (MODEFET) and developed as an ultra-high-speed electronic device or a milliwave-microwave electronic device.
A typical example of this heterojunction field effect transistor uses InP as a semiconductor substrate, InGaAs as a channel layer, and InAlAs as a barrier layer. This InAlAs-InGaAs HEMT has excellent high-frequency characteristics resulting from high electron mobility obtained by InGaAs and high electron density obtained by a large conduction band energy difference between InAlAs and InGaAs.
FIG. 6 shows a typical structure of a conventional heterojunction field effect transistor. Referring to FIG. 6, a 200-nm In.sub.0.52 Al.sub.0.48 As buffer layer 4-1, a 15-nm In.sub.0.53 Ga.sub.0.47 As channel layer 4-2, a 3-nm In.sub.0.52 Al.sub.0.48 As spacer layer 4-3, a 5-nm In.sub.0.52 Al.sub.0.48 As carrier supply layer 4-4 doped with 1.times.10.sup.19 cm.sup.-3 of Si as a dopant, a 10-nm In.sub.0.52 Al.sub.0.48 As Schottky barrier layer 4-5, and a 15-nm In.sub.0.53 Ga.sub.0.47 As cap layer 4-7 doped with 1.times.10.sup.19 cm.sup.-3 of Si as a dopant are formed in this order on an InP semiconductor substrate 4-0 by a well-known epitaxial growth technique.
Additionally, source and drain regions, e.g., ohmic contact regions of source and drain electrodes 4-8 and 4-9 made from AuGe/Ni or the like are formed on the cap layer 4-7 to oppose each other with a recess OA between them. These source and drain electrodes 4-8 and 4-9 are electrically connected to a two-dimensional electron gas in the channel layer 4-2 via the Schottky barrier layer 4-5, the carrier supply layer 4-4, and the spacer layer 4-3.
The recess OA is formed to separate the source and drain regions. This recess OA is obtained by etching the cap layer 4-7 which is present between the source and drain electrodes 4-8 and 4-9 and is a heavily doped layer. The recess OA is formed by wet-chemical etching using an acid or alkaline solution. When the cap layer 4-7 is removed by this wet-chemical etching, the Schottky barrier layer 4-5 is exposed to form a gate region. Ti/Pt/Au metals are sequentially deposited on the surface of the exposed Schottky barrier layer 4-5 to form a gate electrode 4-10. Regions 4-11 between the source and gate electrodes 4-8 and 4-10 and between the drain and gate electrodes 4-9 and 4-10 are separate regions for separating the source and drain regions.
The properties of the heterojunction field effect transistor shown in FIG. 6 will be described below.
This heterojunction field effect transistor changes the density of the two-dimensional electron gas in the channel layer 4-3 positioned below the gate electrode 4-10 by the voltage applied to the gate electrode 4-10, thereby controlling the current flowing between the source and drain electrodes 4-8 and 4-9.
An important factor by which the performance of this heterojunction field effect transistor is determined is the parasitic resistance in the regions (i.e., the separate regions 4-11) formed between the cap layer 4-7 and the gate electrode 4-10 when the recess OA is formed.
In these separate regions 4-11, the cap layer 4-7 is removed, and the surface of the Schottky barrier layer 4-6 is exposed to form a high surface state. Accordingly, of carrier electrons supplied from the carrier supply layer 4-4, the ratio of electrons decreased by a surface depletion layer becomes higher than in other regions, and the two-dimensional electron gas density in the channel layer 4-3 becomes lower than in other regions. Consequently, the parasitic resistance increases to deteriorate the transistor performance such as the transconductance or the cutoff frequency.
To improve the performance of the heterojunction field effect transistor, therefore, it is necessary to decrease the size of the separate regions 4-11.
On the other hand, the breakdown voltage of a transistor is determined by the reverse breakdown voltage between the gate and drain. That is, when the separate regions 4-11 are small, the voltage applied between the gate and drain is concentrated in these narrow separate regions 4-11, and this significantly decreases the breakdown voltage.
Accordingly, to increase the breakdown voltage of the heterojunction field effect transistor, it is necessary to increase the size of the separate regions 4-11.
As described above, the conditions by which the performance and the breakdown voltage of the heterojunction field effect transistor are improved are contradictory to each other. No conventional methods can satisfy these Fonditions at the same time.
Also, the two-dimensional electron gas density in the carrier layer immediately below the separate regions 4-11 cannot be externally controlled by, e.g., the voltage applied to the gate electrode 4-10 or other electrodes. Therefore, care must be taken in designing the epitaxial layer structure so that the two-dimensional electron gas density in the separate regions 4-11 is well maintained.
From the foregoing, it is difficult to fabricate a heterojunction field effect transistor having a threshold voltage at which the channel is pinched off with no bias applied. In other words, in a heterojunction field effect transistor using electrons as carriers, it is difficult to fabricate a heterojunction field effect transistor whose threshold voltage has a positive value (i.e., an enhancement mode HEMT) or a heterojunction field effect transistor whose threshold voltage has a negative value close to 0 V.
FIGS. 7A and 7B are views for explaining a conventional method by which the above difficulty is eliminated. Referring to FIGS. 7A and 7B, the epitaxial layer structure is so designed as to have a sufficiently large negative threshold value when the cap layer 4-7 is removed. The cap layer 4-7 is removed by wet-chemical etching using an acid or alkaline solution to form the recess OA. Thereafter, Pt/Ti/Pt/Au metals are sequentially arranged as the gate electrode 4-10 on the surface of the Schottky barrier layer 4-5. FIG. 7A shows this state.
Additionally, the wafer is annealed at 250.degree. C. to diffuse Pt of the gate electrode into the Schottky barrier layer 4-5. Consequently, as shown in FIG. 7B, the effective thickness of the Schottky barrier layer 4-5 is decreased only in a portion immediately below the gate. This allows the separate regions 4-11 to hold sufficiently high two-dimensional electron gas density.
In this method, however, the controllability of Pt diffusion by anneal is poor, so the threshold value of each device is difficult to control. Accordingly, the in-plane uniformity of each device on the wafer cannot be ensured.
As a method of assuring the in-plane uniformity, Japanese Patent Laid-Open No. 6-120258 has disclosed a method which uses an etching stopper layer to decrease the effective barrier layer thickness in a region immediately below the gate with high reproducibility. That is, this method exposes the gate electrode formation surface with high reproducibility by using different etching solutions having high selectivity to two layers sandwiching the etching stopper layer.
Since, however, selective wet-chemical etching is used to remove the etching stopper layer, the section of the recess in the etching stopper layer is extended by side-etching. Consequently, the Schottky barrier layer is exposed around the gate electrode, and this undesirably increases the parasitic resistance.
As described above, when a metal (Pt) of the gate electrode is diffused by anneal in the conventional method, the threshold voltage of each device is difficult to control because the controllability of Pt diffusion is poor.
Additionally, when the etching stopper layer is used, wet-chemical etching is used to remove the etching stopper layer. This extends a region where the Schottky barrier layer is exposed around the gate electrode, undesirably increasing the parasitic resistance.